Input 10M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um SP/FSG Logic process. View PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG ...

Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process. View PLL ...