Platform Development Models In order to meet these requirements we examine microarchitectures and design environments. Because of the need for flexibility and high levels of parallel execution two ...

Each operation of сore has execution time not more than one cycle so its architecture is RISC. The core is based on VLIW architecture with 132-bit instruction. This instruction consists of following ...

In this paper, we propose a coprocessor architecture which is specifically designed to perform machine vision related operations at the edge using very long instruction word (VLIW) architecture. It ...