2023年3月8日 · GitHub Action ghdl/setup-ghdl-ci created, to allow easy installation of nightly GHDL assets in GitHub Actions workflows. Main documentation site (s) moved to ghdl.github.io/ghdl and ghdl.github.io/ghdl-cosim.

To compile all source files with GHDL, the simulator executable is searched in PATH. The found default GHDL executable can be overwritten by setting the environment variable GHDL or by passing the parameter --ghdl (Bash) or -GHDL (PoSh) to the scripts.

Invoking GHDL ¶ The form of the ghdl command is ghdl command [options...]. There are multiple available commands, but these general rules apply: The first argument selects the command. The options are used to slightly modify the action. No option is allowed before the command.

GHDL can be downloaded as a tarball / zipfile or cloned with git clone from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the Sources page for further details.

Quick Start Guide ¶ Since this is the user and reference manual for GHDL, it does not contain an introduction to VHDL. Thus, the reader should have at least a basic knowledge of VHDL. A good knowledge of VHDL language reference manual (usually called LRM) is a plus.

Simulation (runtime) ¶ Simulation options ¶ In most system environments, it is possible to pass CLI options while invoking a program. Contrary to most programming languages, there is no standard method in VHDL to obtain the arguments or to set the exit status. However, the GHDL runtime behaviour can be modified with some options:

GHDL is a shorthand for G Hardware Design Language (currently, G has no meaning). It is a VHDL analyzer, compiler, simulator and (experimental) synthesizer that can process (nearly) any VHDL design.

ghdl-yosys-plugin is a module to use GHDL as a VHDL front-end for Yosys Open Synthesis Suite, a framework for optimised synthesis and technology mapping. Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification, etc.

First, you have to compile the file; this is called analysis of a design file in VHDL terms. Run ghdl -a hello.vhdl in the shell. This command creates or updates a file work-obj93.cf, which describes the library work. Then, run ghdl -e hello_world in the shell.

Option 1. Take COSIM_FUNCTION and put all your Verilated models inside. That is, let GHDL be the root, and evaluate the C++ models with a fixed frequency (in terms of simulation time). See ghdl#1335, where a user reported co-simulating microwatt (VHDL) and …