Description: DUAL J-K FLIP FLOP WITH CLEAR. Manufacturer: STMicroelectronics.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.

Jameco Electronics 74107 Logic IC, Flip Flops. Products in stock and ready to ship. Quotes, samples and datasheets available at Jameco Electronics.

74107 Datasheet(HTML) 1 Page - STMicroelectronics : zoom in zoom out 1 / 11 page. M54HC107. M74HC107. October 1992. DUAL J-K FLIP FLOP WITH CLEAR. B1R (Plastic Package) ORDER CODES : M54HC107F1R. M74HC107M1R. M74HC107B1R. M74HC107C1R. F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN …

The M54/74HC107 is a high speed CMOS DUAL JK FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input a.

54/74107 54LS/74LS107 DUAL JK FLIP-FLOP (With Separate Clears and Clocks) DESCRIPTION— The ’107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transi­

74107 IC Dual JK Flip-Flop. The 74HC107 is a JK Flip-Flop with individual J, K, Direct Clear, and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation.

Download 74107 Datasheet. File Size: 248.85 Kbytes. Part #: 74107. Description: DUAL J-K FLIP FLOP WITH CLEAR. Manufacturer: STMicroelectronics.

It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs.

DESCRIPTION The is a high speed CMOS DUAL JK FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse.