2024年9月23日 · 在AI需求提升的背景下，SerDes技术向224G升级的趋势加速确立，对应传统系统总线如PCle、SAS，通信总线如InfiniBand、以太网等的信号传输速率持续提升。 据光大证券，2010年SerDes能做到10Gbps的传输速度,而2019年这一要求便已经提升到约112Gbps。 Marvell在FQ4 2024业绩电话会上表示，其下一代单通道200Gb/s速率的1.6T PAM DSP产品已经在客户侧进行认证，预计将于今年年底开始部署。 英特尔也展示了其自研的3nm SerDes芯片， …

The emergence of cloud computing, machine learning, and artificial intelligence is gradually saturating network workloads, necessitating rapid growth in datacenter bandwidth, which approximately doubles every 3–4 years. New electrical interfaces that demand dramatic increases in SerDes transceiver speed are being developed to support this. This paper presents a power-efficient 224Gb/s-PAM-4 ...

受 AI 智能算中心的驱动，基于4x112G的400G 光模块，和基于8x112G的800G的光模块已经很成熟了，标志就是大家都在降本增效，考虑干掉功耗的DSP，...另外一个标志就是2024 CIOE深圳光博会，在很多大厂的展台800G光模块已经不再是C位了，在众多规模较小的厂商展台400/800G已大量涌现。 CIOE光通信部分火热的主题之一是“1.6T” 1.6T = 16 lane电接口 x 112G， +oDSP Gearbox 2:1，实现光链路的8x224G PAM4. 1.6T = 8 lane电接口 x 224G， 1:1， 光链路也是跑 …

112G 和 224G SerDes 之间的信号损耗对比揭示了有趣的见解。 随着奈奎斯特频率翻倍，224G 面临着为给定信道或距离类型提供更高性能的挑战。 224G 的引入不仅意味着数据传输速率的飞跃，而且还需要在克服信号丢失和降低功耗方面取得实质性进展。

2024年2月26日 · 英特尔之前曾在 IEEE 活动中展示过 224 Gb/s，传输 (Tx) 为每比特 1.9 皮焦耳，接收 (Rx) 为每比特 1.4 皮焦耳（合计 3.3 pJ/位）。 现在，当每秒传输 GB 字节时，该值可能很高 - 以 3.3 pJ/bit 的速度传输 1 Terabit 相当于 3.3 瓦。

The Cadence 224G SerDes PHY enables the emerging 1.6T and 800G networks for hyperscale data center and artificial intelligence (AI) infrastructures. The IP incorporates industry-leading digital signal processing (DSP) SerDes technology to support LR, MR, and VSR at 1.25 to 225Gbps data rates.

2025年2月19日 · 224G SERDES is a high-speed interface technology that underpins next-generation 1.6Tb links. Getting 224G signals from the ASIC to the interconnect and beyond remains a key challenge for the deployment and scaling of 1.6Tb. Each 1.6Tb link uses 8 …

2022年1月19日 · This article explains the requirements for a 224Gbps electrical interface, including channels, signal modulation and SerDes technology, in next-generation high-performance computing (HPC) designs.

High-speed SerDes interface serves as a fast and reliable external connectivity between semiconductor chips. Connection length in the chip-to-chip or chip-to-module applications is less of a concern at 224Gbps data rate and PAM4 modulation is widely adopted.

The CEI-224G Interconnect Framework explores the interconnect needs for next generation systems and identifies applications for possible work at the OIF or other standards bodies to address the industry’s next generation needs.