
CD74HCT259 data sheet, product information and support | TI.com
TI’s CD74HCT259 is a High Speed CMOS Logic 8-Bit Addressable Latch. Find parameters, ordering and quality information.
The CDx4HC(T)259 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers.
CD74HCT259 数据表、产品信息和支持 | 德州仪器 TI.com.cn
TI 的 CD74HCT259 是一款 高速 CMOS 逻辑 8 位可寻址锁存器。 查找参数、订购和质量信息.
The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for general-purpose storage applications in digital systems. They are multifunctional devices capable of storing single-line data in eight addressable latches.
74HCT259PW,112_Nexperia (安世)_74HCT259PW,112中文资 …
74HCT259PW,112价格参考¥1.68。 下载74HCT259PW,112中文资料、引脚图、Datasheet数据手册,有锁存器详细引脚图及功能的应用电路图电压和使用方法及教程。
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states.
74HC259D (8-bit addressable latch) | Nexperia
74HC259D - The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states.
74HC259; 74HCT259 | Nexperia
All type numbers in the table below are discontinued. If you are in need of design/technical support, let us know and fill in the answer form we'll get back to you shortly. As a Nexperia …
CD74HCT259E Texas Instruments | 集成电路(IC) | DigiKey 市场
来自 Texas Instruments 的 CD74HCT259E – D 型,可寻址 1 通道 1:8 IC 标准 16-PDIP。 DigiKey 提供数以百万计电子元器件的定价和供应信息。
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states.
- 某些结果已被删除