Hi, I need to use an AXI Memory-Mapped Master Inf in the FPGA, and i tried to use the AXI Master Burst logiCORE under the influence of youtube videos from Mohammadsadegh Sadri . A

Hi @nikhilthapa (Member) Thank you for your reply. It is assumed that the result calculated in the FPGA will be output as an image at the end. It's not a pattern image.

This issue has been addressed in FIFO Generator v4.3. We strongly recommend an upgrade to v4.3, but if this is not possible please use the following information: This issue occurs

Hi there, I am trying to get VPSS example design to work on my ZCU106 board. I did everything exactly same as what it says in VPSS product guide and created the example design, sy

vcu :2020.1. failed: GStreamer-CRITICAL **: 08:46:38.851: gst_buffer_peek_memory: assertion 'idx < len' failed. #include <gst/gst.h> #include <stdio.h> #include ...

Each channel needs to be correctly connected to the corresponding common block for the quad that the channel is in. When the starting GT channel for the core is channel 3 of 4 in

Sorry I am new to all this. I am trying to locate the omxh264enc and dec for the zcu104. Would someone be able to tell me what I need to download?

**BEST SOLUTION** 请排查一下pcie 和aurora 是否共享了GT 的位置？ 包含时钟，看一下GT 是包含在example design 还是IP 里面的 是否有矛盾. 另外可p

Don't see what you're looking for? Ask a Question. Get Support. Community Feedback Survey. Adaptive SoC & FPGA Support

@2U3aga1. Table 1-55 in UG471(v1.10) is your go-to reference for IOSTANDARDs in Xilinx 7-Series FPGAs. About HSUL_12, Table 1-55 says: it can be used in both HR and HP banks; when