The AMD LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft AMD Intellectual Property (IP) core for use with the Vivado™ Design Suite. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol.

AXI DataMover v5.1 7 PG022 April 26, 2022 www.xilinx.com Chapter 1:Overview Feature Summary AXI4 Compliant The AXI DataMover core is fully compliant with the AXI4 interface and the AXI4-Stream interface. AXI4 Data Width The AXI DataMover core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and 1,024 bits. AXI4-Stream Data Width

AXI DMA Controller: v7.1: AXI4 AXI4-Stream AXI4-Lite: Vivado™ 2024.1: Versal™ adaptive SoC Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix 7 Kintex 7 Virtex 7: AXI DMA Controller: v6.03a: AXI4 AXI4-Stream AXI4-Lite: ISE™ 14.4 EDK™ 14.4: Zynq 7000 Artix 7 Kintex 7 ...

The AXI Datamover is a key building block for the AXI DMA core and enables 4 kbyte address boundary protection, automatic burst partitioning, as well as providing the ability to queue multiple transfer requests using nearly the full bandwidth capabilities of the AXI4-Stream protocol.

This session describes the process for building a software system that allows DMA functionality from user space. This is accomplished using a character mode device driver with a user space application.

• AXI Clock Converter connects one AXI memory-mapped master to one AXI memory-mapped slave operating in a different clock domain. • AXI Protocol Converter connects one AXI4, AXI3 or AXI4-Lite master to one AXI slave of a different AXI memory-mapped protocol. • AXI Data FIFO connects one AXI memory-mapped ma ster to one AXI memory-mapped

The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between the AXI4 and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also offload data movement tasks from the CPU in processor-based systems.

The AXI Bridge with DMA IP core is Smartlogic’s ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces. AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA.

QDMA – A queue based, configurable scatter-gather DMA implementation which provides thousands of queues, support for multiple physical/virtual functions with single-root I/O virtualization (SR-IOV), and advanced interrupt support. In this mode the IP provides AXI4-MM and AXI4-Stream user interfaces which may be configured on a per-queue basis.

Zynq UltraScale+ MPSoC: Embedded Design Tutorial 6 UG1209 (v2018.2) July 31, 2018 www.xilinx.com Chapter 1: Introduction