Compute Express Link (CXL) is an open standard interconnect for high-speed, high capacity central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. [1][2][3][4] CXL is built on the serial PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/outp...

Download an Evaluation Copy of the CXL® 3.2 Specification. Please review the below and indicate your acceptance to receive immediate access to the Compute Express Link® Specification 3.2. COMPUTE EXPRESS LINK CONSORTIUM, INC. EVALUATION COPY AGREEMENT – as of November 10, 2020.

2023年12月8日 · 2019年至今，CXL已经发表了1.0/1.1、2.0、3.0/3.1五个不同的版本，CXL2.0内存的池化（Pooling）功能较好的实现了以内存为中心的构想；CXL3.0则实现Memory sharing（内存共享）和内存访问，在硬件上实现了多机共同访问同样内存地址的能力；而CXL3.1，则具备开启更多对等通信通道的能力，实现了对内存和存储的独立分离，形成独立的模块。 并且新规范将支持目前仍在研发中的 DDR6内存。 并且对于未来，CXL有着非常清晰的技术发展路线图，业界 …

CXL 3.2 Specification Now Available Learn more about the enhancements in security, compliance, and functionality of CXL Memory Device included in the specification. View the Press Release

2024年7月8日 · Table 1 overviews the three current CXL generations versions and key use case examples. The CXL 1.0 multiplexes coherency and memory semantics on top of the PCIe physical layer, as shown in Figure 1. CXL introduces custom link and transaction layers to achieve low latency comparable to remote socket memory accesses.

CXL 1.1 and CXL 1.0. CXL 2.0 enhances the CXL 1.1 experience in three major areas: support for single-level switches, support for persistent memory, memory. pooling, and security. These features enable many devices in a platform to migrate to CXL, while maintaining compatibility with PCIe 5.0 and the low-latency .

5 天之前 · The CXL Consortium has released CXL specification 3.0, expanding on previous versions to increase scalability and optimize system-level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. In addition to memory pooling, CXL 3.0 enables ...

2023年11月14日 · The Compute Express Link™ (CXL™) 3.1 specification introduces CXL fabric improvements and extensions, Trusted-Execution-Environment Security Protocol (TSP), and memory expander improvements.

2022年4月20日 · CXL – Computer eXpress Link – the extension of the PCIe bus outside a server’s chassis, based on the PCIe 5.0 standard. There are five successive versions of the standard; CXL v1, released in March 2019 enables server CPUs to access shared memory on local accelerator devices with a cache coherent protocol; memory expansion.

2024年7月1日 · First introduced back in 2019, the Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as AI accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives.