2022年11月2日 · This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted...

2003年2月12日 · To clarify the thermal/chemical reactions that occur during the introduction of D atoms, we observed chemical structures that con-tain H/D atoms in the interlayer dielectrics using an FTIR. D2 annealing followed by additional an-nealing in N2 or H2 ambient at 450°C was also carried out to check their thermal stabilities.

1994年1月1日 · Hydrogen annealing effects on SiO 2 /Si(100) interface traps and bulk oxide traps have been investigated through deuterium (D 2) anneal of ultra-thin SiO 2 films. The interface traps are annihilated by low-temperature D 2 anneal, whereas high-temperature anneal allows for

2020年7月24日 · High-pressure (HP) deuterium (D 2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n + poly-Si gates.

Reliability of Core and IO FinFET is extensively investigated with various process steps at Fin, Source/ Drain, sacrificial Gate-Metal, and High-Pressure D2 Anneal. By modulating the process knobs, we quantified the effect of oxide traps (at bulk or interface) on reliability mechanisms of replacement metal gate (RMG).

In this study, post-metal annealing (PMA) process with D2 and N2 gases under a high-pressure condition was conducted to verify performance enhancement in gate-enclosed FETs. We explored the trap behaviors inside the bandgap of Si and SiO2 by quantitatively using capacitance-voltage ( C – V ) characteristics.

2022年12月25日 · As compared with conventional forming gas annealing (FGA), a dramatic reduction in the interface state density (D it) was achieved after both H 2 - and D 2-HPA processes at the equivalent temperature (300 °C) and time (30 min) by effectively passivating the Ge-induced dangling bonds at the interface region.

2022年11月1日 · Low-temperature deuterium (D 2) annealing (LTDA) is applied to improve performances and reliability of a MOSFET. The LTDA is performed at 300 °C, which is at least 100 °C lower than the widely used temperature of forming gas annealing (FGA) with H 2, which contributes to reducing a thermal budget especially in the backend-of-the-line (BEOL).

D2 Material Heat Treatment Annealing. D2 tool steel annealing temperature: 870-900 °C (1600-1650 °F), rate of cooling: 22°C (40 °F), hardness: 217-255 HB. Note: The upper limit of the range applies to large sections and the lower limit to smaller sections.

2016年10月1日 · Low-temperature deuterium (D2) annealing (LTDA) is applied to improve performances and reliability of a MOSFET. The LTDA is performed at 300 oC, which is at least...