Extreme ultraviolet lithography (EUVL, also known simply as EUV) is a technology used in the semiconductor industry for manufacturing integrated circuits (ICs). It is a type of photolithography that uses 13.5 nm extreme ultraviolet (EUV) light from a laser-pulsed tin (Sn) plasma to create intricate patterns on semiconductor substrates.

This paper presents a minimum pitch single patterning process for 5nm node back-end-of-line (BEOL) integration based on extreme ultraviolet (EUV) lithography with quasar illumination and optical proximity correction (OPC). OPC was applied for improving stochastic printing failures such as single-line-open (SLO) and micro-bridges.

目前5nm制程的芯片有台积电已经量产的FinFET和在研发的GAA两种，这里只谈FinFET。查阅台积电的road map可知5nm FinFET的X方向的Fin周期(Fin Pitch)大概在28nm左右，Y方向的Gate Pitch(Poly Pitch)大概在51nm左右。用波长13.5nm的EUV曝光出这样的pitch不难吧？那5nm制程代 …

EUV 光刻机得益于使用13.5nm EUV 作为光源，单次曝光的分辨率极限可以达到13nm，因此在7nm 制程工艺中的特征尺寸基本单次曝光（Single Expose）就可以完成。EUV 同样可以使用SADP 技术，实现更小的特征尺寸，使得芯片制程工艺向5nm/3nm 继续发展。 ASML EUV

2024年2月28日 · Extreme ultraviolet (EUV) lithography is the leading lithography technique in CMOS mass production, moving towards the sub-10 nm half-pitch (HP) regime with the ongoing development of the next generation high-numerical aperture (high-NA) EUV scanners.

2017年2月2日 · We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time.

Abstract: Extreme ultraviolet (EUV) lithography has emerged as a promising candidate for the manufacturing of semiconductor devices at the sub-14nm half pitch lines and spaces (LS) pattern for 7 nm node and beyond. The success of EUV lithography for the high volume manufacturing of semiconductor devices depends on the availability of suitable ...

2024年11月12日 · In this paper, we experimentally tested various ways to reduce EUV dose for CAR and MOR to print pitch 28nm line-space structures while minimizing the impact on LER and defectivity. The impact of several tuning knobs for dose reduction was explored: resist formulation, post-exposure pattern rectification, underlayer, post-exposure bake (PEB ...

• The EDA infrastructure for EUV lithography is maturing. • SRAFs • Flare • Compensation for pitch-dependent focus resulting from oblique illumination geometry. • Maximizing NILS for better LER. multilayer reflector OPC for EUV

Much optimization of EUV resists is still needed, and it is early to predict final performance capability of EUV resists. However initial results show promising results for high sensitivity resists.