For lateral isolation of transistors, a so-called field oxide (FOX) is deposited on the bare silicon surface. While the oxidation on the bare silicon takes place, the pad oxide causes a lateral diffusion of oxide beneath the silicon nitride and thus a …

The FOX is used to isolate the devices from one another (the active areas are isolated by the FOX). Note that there will be some resistive connection between active areas (either through the substrate or the n-well). However, the FOX is grown thick enough to keep the interactions between adjacent active areas to a minimum.

大规模集成电路（Large-Scale Integration，LSI）是一种在微电子领域中使用的概念，指将大量数目的 晶体管 和其他电子元件集成在一个单一的芯片上。 这项技术被广泛应用于电子设备中，很大程度上促进了计算机、通信和其他电子产品的发展。 大规模集成电路技术最早于20世纪60年代发明，初始目的是实现更高的电路密度和更好的性能。 在早期，集成电路中的晶体管数量通常在几十或几百个之内。 但随着技术的不断发展，现代的大规模集成电路中通常包含数亿个晶体管。

本课程旨在填补数字信号处理（DSP）算法和超大规模集成电路（VLSI）设计之间的空白，介绍DSP系统定制或半定制VLSI电路设计所需的方法。 该课程可视为顶层（包含算法层和架构层）VLSI设计课程。 本课程的重点是如何针对给定的DSP应用（例如，纠错编码，MPEG解码等）设计高效的架构、算法和电路，这些设计会在高速、低功耗或低硬件面积方面针对实际应用需求做出相应优化。 《数字大规模集成电路》 课程编号：71020023. 内容：

2020年4月17日 · 7. • For lateral isolation of transistors, a so-called field oxide (FOX) is deposited on the bare silicon surface. While the oxidation on the bare silicon takes place, the pad oxide causes a lateral diffusion of oxide beneath the silicon nitride and thus a slight growth of oxide at the edge of the nitride mask.

超大规模集成电路 （英語： Very large-scale integration， 縮寫： VLSI），是一种将大量 晶体管 组合到单一芯片的 集成电路，其集成度大于 大规模集成电路。

• Algorithm and architecture level optimization • VLSI signal processing – Multipliers and adders, scheduling and binding of datapaths, low power designs, re-configurable DSP

Abstract: A more reliable process for near-zero bird's beak and fully recessed field isolation structure has been developed, which effectively reduces the narrow channel width effects which exist in the conventional local oxidation of silicon (LOCOS) processing.

VLSI Circuit Design Processes: VLSI Design Flow (Y-Chart), MOS Layers, Stick Diagrams, Design Rules and Layout, Lambda(λ)-based design rules for wires, contacts and Transistors, Layout Diagrams for NMOS and CMOS Inverters and Gates.

Extraction of interconnect capacitance in modern VLSI technology is very complicated because of Non-homogenous dielectric (etch stop, barrier liner, etc.) Complex pattern of neighboring interconnects (need 3D modeling) There are two types of capacitances: Ground capacitances Coupling capacitances