Sphinx Extension which generates various types of diagrams from HDL code, supporting Verilog, nMigen and RTLIL. sphinxcontrib-hdl-diagrams is a Sphinx extension to make it easier to write nice documentation from HDL source files. It primarily uses Yosys to read the source files and generate the diagrams. Check out the documentation for examples.

Diagram detailing the three key stages of the HDL lifecycle. (1) Synthesis: ApoA1 is synthesized in the liver and the gut, where it can be gradually lipidated on-site or by the adipose tissue...

Learn core operations of HDL Design Series, how to administer it for team operations and how to implement your company design guidelines for RTL coding. HDL Designer assists engineers in analyzing, assessing, and visualizing complex RTL designs, providing code integrity and connectivity analysis.

Facilitating an abstraction level between block diagrams and plain HDL code, the block diagram editor allows you to graphically represent cooperating VHDL processes or Verilog always statements. The processes can be implemented using state diagrams, truth tables or HDL text.

If your HDL design is in large part structural, it may be easier for you to enter its description graphically as a block diagram, rather than typing hundreds of source code lines. The Block Diagram Editor will then convert the diagram automatically into …

HDL-SCHEM-Editor can generate HDL-code (VHDL, Verilog, SystemVerilog) from the schematic. HDL-SCHEM-Editor can link the generated HDL-code from the "Generated HDL"-Tab to the schematic. HDL-SCHEM-Editor can link the compiler messages in the "Compile Messages"-Tab to the schematic or to the "Generated HDL"-Tab.

High-density lipoprotein (HDL) plays an important role in lipid metabolism and especially contributes to the reverse cholesterol transport pathway. Over recent years it...

Graphical HDL Design tool for VHDL and (System)Verilog. Combines block diagrams, state diagrams, truth tables and HDL code. Supports user defined types in packages, configurations, generics, generate statements and more. It will give you a complete overview of any VHDL or Verilog design in seconds.

The state diagram editor supports Moore, Mealy and mixed state machines. Any valid VHDL expression or Verilog statement can be used to define actions and transition conditions. Transitions can be synchronous or asynchronous; outputs can be clocked or combinatorial.

hdl-diagram¶ The hdl-diagram RST directive can be used to generate a diagram from HDL code and include it in your documentation...