2011年5月29日 · Below, see a timing diagram with the bit clock (bottom), LR clock (top) and the data on the codecs serial port output. The serial clock has 6.144 MHz, the format is I2S, LR clk is 1/64 of the bit clock. I overdrive one of the codec's inputs so that the data at the output is 0x7FFFFF which can be seen in the timing diagram.

2017年11月16日 · I copied the contents of the axi_i2s_adi_constr.xdc file into the top level design constraints file and modified the first two lines as shown below. The constraints are now applied and the Vivado 2017.2 design now meets timing.

2021年10月22日 · I route I2S signals to the external DACs, and I notice that there is an unexpected delay of ≈5ns for the DATA in relation to BCLK and FS. My DAC's do not like this, so I had to tweak the circuit by adding a small capacitor to the BCLK pins on the DAC to make it work.

2021年5月27日 · I can successfully compile the zed board version of the AD7768 eval project. If I make a few modifications, like adding ILA probes, I starting getting timing failures in the AXI I2S ADI IP Core. The timing failures appears to be between the ~12MHz clock of the data clock with the 100MHz AXI clock.

2019年5月5日 · Hello Specialist, \\n \\n I am implementing the schematic design for the ADV7619 part, I am very confused about the pin assignments when it is configured as I2S mode. Please help to clarify here. \\n \\n In your latest revision D datasheet, in the pin description on Page 12, you don\\u0026#39;t mention AP1 can be configured as I2S data. On the other hand, In Figure 5 I2S Timing, you specify ...

2017年8月8日 · I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq+ (ZCU102 ES1 Board) Vivado 2017 design and it is failing timing. See below. Can you help?

2023年8月28日 · Dear developers, \\n \\n I am trying to connect 6 digital microphones to the adau1467 evaluation board. The microphones are all INMP441 on a breakout board. \\n They are connected to SDATA, LRCLK and BCLK at IN0 and IN3 at J8 and IN1 at J5. L/R of the mic\\u0026#39;s are connected in pairs to 3.3v and 3 to 0v, so I have 3 stereo sets. \\n The first test to try is confirming that the ...

2017年12月3日 · Using the I2S input interface, if I reproduce an audio file with a sample rate of 96kHz/24 bit stereo, the LRCLK of audio source is 96kHz, the DSP is set to 48kHz, is there a missmatching?

2019年11月25日 · Is it correct？ 2，default Word Length is 24bit，but LRCLK = BCLK / 64，when LRCLK is high or low，the word length is 32bit 。 so, when Word Length is 24bit，the lower 8 bits is NULL？ 3，according to datasheet, we use I2S timing, but nothing output 。 MCLK In is 12.288，AD1933 MCLK Out is 12.288 too,。

2022年5月16日 · Your setup is not correct for I2S but with those settings you compensated for timing issues. The BLCK should be falling edge and you should have 1BCLK delay at the start of the frame. That is the standard for I2S. Your experiments show that it is simply a timing issue which goes back to having good clean edges of the clocks.