2019年1月23日 · Electrostatic Discharge (ESD) Many products use parts that are known to be sensitive to electrostatic discharge (ESD), or static electricity. Any computer part containing transistors or integrated circuits (ICs) should be considered sensitive.

2009年10月30日 · When holding or installing electrostatic discharge-sensitive (ESD) parts, use the ESD handling kit (IBM® part 6428316) or similar. Read the instructions inside the top cover of the carrying case. All system logic cards are sensitive to electrostatic discharge.

2010年12月24日 · We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers.

Calculated on the ED and ER records, required input to LD. ESD_TYPE is further qualified by ESD_SCOPE. Binder-generated ESD type.

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S-parameter test structures from a 45nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42fF/μm, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction.

Attention: Many of the field replaceable units (FRUs) are sensitive to electrostatic discharge (ESD), and can potentially be damaged by improper handling. When working with any FRU, use correct ESD precautions: Attach ground to the indicated area on the chassis

为了表征人体带静电并接触器件放电的电路特性，以及半导体器件的ESD敏感度，相关标准组织/机构制定了人体模型（Human Body Model-HBM）以规范HBM模式下的ESD测试模型和等级标准。 人体放电模型 (HBM)的ESD是指因人体在走动摩擦或其它因素在人体上累积了静电，当此人碰触到IC时，人体上的静电便会经由IC的引脚 (pin)而进入IC内，再经由IC放电到地。 如左下图所示。 放电的过程会在短到几百纳秒 (ns)的时间内产生数安培的瞬间放电电流，此电流会把IC内的组件 …

2024年1月6日 · ESD (Electrical Static Discharge) 产生的原因多种多样，对 集成电路 放电的方式也有所不同。 为了保证集成电路产品的良率，提高可靠性，需要对电路ESD防护能力进行测试。 一般测试分为两类： 样品研究型测试 和 产品通过型测试： （1）样品研究型测试：在芯片的研发阶段，研究器件 ESD 防护的 功能测试。 此阶段的测试广泛采用传输线脉冲技术（TLP）。 通过TLP测试，可以获得防护器件的关键性能参数，便于在生产制造过程中调整相关的设计，从根 …

In IBM, an NVRAM ESD network, with BJT and CMOS components, utilizes a lateral STI-defined pnp BJT ESD network with a dual-oxide PFET well-bias controller to provide sequence independence between the power programming pin and power supply.