55V Single N-Channel Power MOSFET in a TO-220 package. Unfortunately, your browser does not support embedded frames (iframes): You can view the embedded page here.

IRFZ24NPBF是一款55V单N沟道HEXFET®功率MOSFET，采用先进的平面技术，具有极低的导通电阻，以及快速开关性能。 立创商城IRFZ24NPBF型号页面提供型号详细中文资料，PDF数据手册在线查看和下载,中文参数，引脚图，代替型号和在线购买等信息。 买IRFZ24NPBF型号,上立创商城.

Fifth Generation HEXFET® power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area.

IRFZ24N由Infineon (英飞凌)设计生产，立创商城现货销售。 IRFZ24N价格参考￥3.7。 Infineon (英飞凌) IRFZ24N参数名称：类型：1个N沟道；漏源电压 (Vdss)：55V；连续漏极电流 (Id)：17A；导通电阻 (RDS (on)@Vgs,Id)：70mΩ@10A,10V；阈值电压 (Vgs (th)@Id)：4V@250uA；栅极电荷 (Qg@Vgs)：20nC@10V；输入电容 (Ciss@Vds)：370pF@25V。 下载IRFZ24N中文资料、引脚图、Datasheet数据手册，有场效 …

下载IRFZ24NPBF中文资料、引脚图、Datasheet数据手册，有场效应管 (MOSFET)详细引脚图及功能的应用电路图电压和使用方法及教程。

accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on- D 2 Pak TO-262. resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application.

N-channel enhancement mode standard level field-effect power transistor in a plastic envelope using ’trench’ technology. The device featuresverylowon-stateresistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in switched mode power supplies and general purpose switching applications. MIN. MAX. MIN. MAX.

立创商城提供minos(迈诺斯)的场效应管(mosfet)irfz24n中文资料,pdf数据手册,引脚图,封装规格,价格行情和库存，采购irfz24n上立创商城

IRFZ24N Fifth Generation HEXFET® power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer

Fifth Generation HEXFET® power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area.