Broadcom’s PCIe Gen 6 connectivity portfolio, which features its new high-port PCIe switch and retimer, help simplify interoperability and system design with its advanced telemetry and diagnostics capabilities. The Broadcom connectivity portfolio utilizes its in-house SerDes, also used in custom XPUs.

Broadcom has further extended its multi-generational PCIe leadership by allowing early access to its PCIe Gen 6 Interop Development Platform (IDP), which simplifies interoperability and system design with its advanced telemetry and

This new generation of the ubiquitous PCIe standard brought with it many exciting new features designed to boost performance for compute-intensive workloads including data center, AI/ML and HPC applications. PCIe 6.0 has now evolved to version 6.1 of the standard. Find out all about PCIe 6.1 in the article below. Contents. What is PCIe 6.1?

2025年2月25日 · Broadcom’s PCIe Gen 6 and CXL 3.1 integrated MAC and PHY retimers extend the reach between a root complex and endpoint by >36 dB of loss at 64 GT/s. Each lane is capable of multiple data rates, including Gen 6 (64G PAM4), Gen 5 (32G), Gen 4 (16G), Gen 3 (8G), Gen 2 (4G) and Gen 1 (2.5G).

2025年2月25日 · Broadcom has further extended its multi-generational PCIe leadership by allowing early access to its PCIe Gen 6 Interop Development Platform (IDP), which simplifies interoperability and system design with its advanced telemetry and diagnostics capabilities.

2023年6月13日 · Although PCIe 6.0 is complete on a design level, no PCIe 6.0 devices have yet come out, but in its latest presentation, PCI-SIG says the next-generation data link should start showing up...

2025年2月25日 · Broadcom is developing a PEX 90144 PCIe Gen 6 switch and two retimers: the BCM85668 8-lane and BCM85667 16-lane products. Retimers are PCIe bus relay stations, receiving a signal, cleaning it up, fixing any degradation, and sending it onward. They enable the bus to operate over longer distances than otherwise.

•Introduction to PCI Express® Specification •Key Metrics and Requirements for PCIe® 6.0 Architecture •PAM-4 and Error Assumptions / Characteristics •PCIe 6.0 Specification Approach to Error Handling: FEC and CRC + Retry •Flit Mode in PCIe 6.0 Specification •Low Power enhancements: L0p •Performance and Reliability results ...

2025年3月27日 · Marvell announced in collaboration with TeraHop, a global optical solutions provider for AI driven data centers, the demonstration of the industry’s first end-to-end PCIe Gen 6 over optics in the Marvell booth #2129 at OFC 2025. The demonstration will showcase the extension of PCIe reach beyond traditional electrical limits to enable low-latency, standards-based AI scale-up infrastructure.

2024年5月30日 · PCIe Gen 6, which operates at 64 gigatransfers-per-second (GT/s), is the first PCIe standard to use four-level pulse-amplitude modulation (PAM4) signaling, displacing the non-return to zero (NRZ) modulation used for the last 20 years.