Oct 20, 2021 · I have seen the abbreviation PHY beeing used for a handful of different things within the context of Ethernet: a PHY is a type of Ethernet physical layer (eg. 100BASE-TX, 10BASE-T) a PHY is an Ethernet transceiver IC (eg. an IC that converts 100BASE-TX to MII/RMII) a PHY is a physical layer device (more than just the transceiver IC)

Apr 5, 2015 · I need to design a 10/100/1000 BASE-T “backplane” board that contains multiple PHY outputs from Ethernet controller chips. On the board ,the LAN specifications are very strict in regard to how the LAN silicon(PHY) is situated to the magnetics and the RJ-45 connectors.

Jul 11, 2013 · A PHY chip or layer converts data between a "clean" clocked digital form which is only suitable for very-short-distance (i.e. inches) communication, and an analogue form which is suitable for longer range transmission. It has no particular clue as to what any of the bits "mean", nor how they should be interpreted or assembled.

Oct 5, 2020 · It's also very possible that only the PHY or the MAC offers a matched output impedance, in this case, the outputs on the unmatched device still needs to be source-terminated on one end. 3. Use the PHY delay option for RGMII clock signals. If the RGMII traces are length-matched, it should work with the default 2 ns delay..

Nov 2, 2024 · I'm reading Analog Device's Beginner's Guide to Ethernet. It's really good and goes into concepts like Manchester Encoding, 4B/5B, NRZT, MLT3 which seem to make sense to me.

Jul 11, 2018 · This specific datasheet doesn't specify what the value for the RSET resistor should be. But after a bit of looking around, I found another datasheet, page 8 for a Realtek IC (PHY) which uses a bandgap reference as well and they use a value of 2.49k for that resistor. The regulator voltages are about the same for both ICs (1.05V vs 1.0V).

Aug 14, 2022 · Generally, if I'm connecting a PHY to RJ45 connector, I would add center tap capacitors and Bob-Smith termination like below. But if I am connecting a PHY to another PHY, do I still need the Bob-Smith termination? Or can I just have center tap capacitors on both sides like below? Both PHYs share same GND but are powered by different rails.

Dec 16, 2022 · PHY requires some fairly beefy pin drivers as well as analog signal processing on the receive side. The fabrication processes to support this well are not optimized for high-density digital logic, which is what the MAC and the rest of the system require. The PHY also dissipates a significant amount of power all by itself.

I have the choice of one of my PHY, but the other is embedded in an as-yet-unspecified PCIe to Ethernet IC (perhaps Gigabit but used in 100 Mbit/s mode), and it is critical that this PHY thinks there is a bona fide 100 Mbit/s Ethernet connection. I could use the following. simulate this circuit – Schematic created using CircuitLab

Jan 10, 2013 · It looks like you have isolated the PHY's power nicely with L10 and bypass caps C69-C74. All you need to do is connect all the PHY grounds together, then make sure that net has exactly one connection to the main ground. That keeps the nasty high frequency loop currents local, but still gives the PHY the same 0V reference as the rest of the board.