PSL is a well structured, layered language. It has four layers viz. boolean, temporal, verification and modeling layer. Each layer brings in a unique expressiveness to PSL. These layers are described in detail in later sections. A few quick start examples are shown below to demonstrate the concept of building PSL properties using individual layers.

PSL is defined in 4 layers: the Boolean layer, the temporal layer, the modeling layer and the verification layer. The Boolean layer is used for describing a current state of the design and is phrased using one of the above-mentioned HDLs.

2014年5月22日 · PSL is defined in 4 layers: the Boolean layer, the temporal layer, the modeling layer and the verification layer. The Boolean layer is used for describing a current state of the design and is phrased using one of the above mentioned HDLs.

PSL is a property language that talks about the design and needs to be linked to a design unit (say RTL model) in order for a tool to check that the design meets the requirements as described by PSL properties. PSL supports a set of verification units as

The PSL language is formally structured into four distinct layers: the boolean, temporal, verification and modelling layers. The verification and temporal layers have a native syntax of their own, whereas the modelling and boolean layers borrow the syntax of the underlying HDL.

The IEEE 1850 Property Speci?cation Language (PSL) is a language for the formal speci?cation of concurrent systems. The language is particularly applicable for writing assertions about hardware designs. PSL supports m- tiple veri?cation paradigms – including formal analysis, simulation, and acc- eration/emulation.

PSL Layers PSL is a Layered Language Boolean Layer The Boolean layer is used to: Specify logic expressions without specific timing information using a standard HDL syntax such as Verilog-HDL and VHDL Example (Verilog): // A and B are mutually exclusive ( !(A & B) ) Example (VHDL): -- A and B are mutually exclusive ( not (A and B) ) Temporal ...

PSL has emerged as one of the standard assertion languages and is on its way to becoming an IEEE standard. This tutorial is intended to get you quickly started on the language. An assertion or property language captures the design behavior spread across multiple clock cycles in a concise, unambiguous manner.

PSL has four layers of specification: Boolean, temporal, modeling, and verification. Notably, the modeling layer is indeed a layer of specification. It doesn’t concern the design of the system but of the auxiliary signals that help express the system design’s temporal properties.

PSL is an abbreviation for Property Specification Language. A property is a boolean-valued fact about a design-under-test. Right now, PSL works alongside a design written in VHDL or Verilog, but in future PSL may be extended to work with other languages.