In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL).

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained.

Continuous scaling of DRAM chips requires further optimization of saddle fin access transistor performance. This paper presents the TCAD simulation studies of the fin structure effects on the threshold voltage, drivability and subthreshold swing.

2021年5月15日 · In this paper, we systematically examined the impact of fin height (HFin) and fin angle (θFin) on the ac performance parameters including total gate capacitance (Cgg), RC delay (CggVDD/ION ...

Abstract: In this paper, a 16nm saddle fin structure was modeled. Active area width (AA CD), AA tapper angle, buried word line trench width (BW CD) and BW tapper angle effects on the device performance were investigated using a built-in drift-diffusion solver.

2009年12月1日 · A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is...

Abstract: In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL).

2021年8月5日 · 在本文中，我们使用 3D TCAD 仿真将传统鞍型 FinFET 与部分隔离型鞍型 FinFET (Pi-FinFET) 进行比较，以检查单电荷陷阱的影响，以正确预测泄漏电流。 我们模拟了漏极区域不同位置的单个电荷陷阱，并分析了陷阱如何影响漏电流。

2022年1月1日 · By combining FinFET with RCAT, S. Park et al. have introduced the saddle-fin cell transistors at the 50-nm technology node, resulting in easy controllability of a threshold voltage, excellent improvement of short channel effects, and superior drivability of on-current [37]. Also, a gate-shielded channel region improves neighbor-gate effects.