SERDES PLL AND Configuration - Q&A - EngineerZone
2024年3月29日 · Hi \\n \\n I am going through A9209 data sheet that refers to AD9081/AD9082 SOFTWARE DEVELOPMENT USER GUIDE \\n \\n I am using the ADC9209 , which means i will be using JESD204BTX part , for that i need to configure the Serdes PLL as well \\n I am making spi controller in fpga , and I am little confused about Serdes PLL Configuration \\n \\n at page number 24 , there is a subsection about ...
SERDES PLL - Q&A - High-Speed DACs - EngineerZone
2024年4月2日 · I am Using AD9152 and I followed the DAC starting sequence with JESD204B Mode 9 , 3.125 Gbps Lane rate. \\n \\n But My SERDES PLL is not locked. Reg 281 shows a value of 101010 . According to the datasheet, PLL is calibrated and reached into lower level of its operating band. What can be the reason for it?
AD9172 SerDes PLL unlocked at ~13G bitrate - EngineerZone
2023年7月11日 · Hello, EZ, \\n dealing with AD9172 DAC at the my custom board I have meet with the absent of locking SerDes PLL (0x281 register) at bitrate range from 12,7 to 13,05 Gbps (first DAC chip) and from 12,65 to 12,85 Gb (second chip). This bitrates correspond required output DAC CLK frequencies 10,16-10,44 GHz and 10,12-10,28 GHz using interpolation by 8 with input IQ-data sample rate near 1,3 GHz ...
Serdes pll is not locked but DLL is locked - Q&A - EngineerZone
2024年11月12日 · Serdes pll now is locked,but sync is not always high when FPGA send 4 K28.5,and we find 0x4B0 =85 0x4B1=86,0x490=09,0x491=09,0x498=FF,0x499=FF,0x4A0=4F,0x4A1=5A,0x4A8=06,0x4A9=04. We use lane 0 and lane1.So what could have led to this result?
AD9173 SERDES PLL Not Locked - Q&A - EngineerZone
0x213: 0x00 % SERDES required register write. 0x280: 0x05 % SERDES required register write. 0x280: 0x01 % Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration. % Can read back reg 0x0281[0]==1 to confirm SERDES PLL lock % ----- Transport Layer Setup, Synchronization, and Enable Links % 0x0308-0x030B is crossbar setup.
AD9154 SERDES PLL not locking - Q&A - EngineerZone
2015年10月6日 · I have a board that uses the AD9154 DAC, and I\\u0026#39;ve been having trouble trying to set up the SERDES PLL. I have a reference clock input of 76MHz, and have the DAC PLL set up so that the VCO is running at 9728 MHz with a DAC clock of 1216 MHz. The DAC PLL is consistently locking without any issues (register 0x084 reads back 0x22). \\n When I try to configure the SERDES PLL, though, it ...
AD9176:DLL and serdes pll are not locked after DAC pll locked
2021年9月9日 · Serdes pll is not locked but DLL is locked Use AD9163,other registers is right,and DLL is locked,so the DAC clock is ok,but we read 0x281 bit0=0, so the serdes pll is not locked and we do not know why.we configure AD9163 by the start up consequence...
AD9163 SERDES PLL locked, but DLL unlocked - EngineerZone
2021年7月8日 · 0x084=0x00 // pll ref clk rate 1x After the start up sequence, the 0x092 was 0x0(dll unlocked), the 0x281 was 0x0B(pll locked). Has some one know the source of this issue?
AD9144/AD9136 FDAC=2GHz，Serdes PLL Unlocked - EngineerZone
2018年7月30日 · 当FDAC=2GHz（仪表：E4438C输入2GHz Tone），Serdes PLL状态为Unlock（ 0x281[0]= 0 ）， 重新校准也没有改善。 请问是否配置有问题，还是其他原因？ Tags: serdes pll Standard High Speed D/A Converters ad9136 jesd204b High Speed D/A Converters =30MSPS ad9144 Show More
Can't get PLL to lock - Q&A - High-Speed DACs - EngineerZone
2024年6月11日 · The SERDES PLL requires a valid clock relationship, as well as a SERDES lane rate that is within the specifications of AD9152. Pages 32-33 give more details for the SERDES PLL. The reference clock to the SERDES PLL (fREF) is not to be confused with the reference clock to DAC PLL (REFCLK). The DAC PLL is different from the SERDES PLL.