2023年10月5日 · Two highly-doped p + silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has...

2025年3月1日 · SET analysis of Si/Si-Ge GAA-NWFET shows that Si-Ge device has 35.85% and 81.38% lower peak currents at C-D junction and source. Si-Ge device shows improved SET response across angle strikes, supply voltages, and channel lengths compared to the Si device.

Abstract—Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can …

A novel modulation-doped field effect transistor (MODFET) with a strain-controlled Ge channel, p-Si/sub 0.5/Ge/sub 0.5//Ge/Si/sub 1-x/Ge/sub x/, is fabricated by molecular beam epitaxy (MBE).

2024年7月22日 · In this paper, we propose a novel Ge/Si1-xGex/Si heterostructure Tunnel FET based sensor which can detect a wide range of biomolecules having dielectric constant ranging from 2.1 to 46.7 in both dry and wet environments. The source is modified by employing a layer of p + Ge material alongside an n + SiGe pocket towards the channel.

2023年4月8日 · This research presents the optimization and proposal of P- and N-type 3-stacked Si 0.8 Ge 0.2 /Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy.

2011年1月1日 · Here, the roles of SiGe can be divided into two categories: one is the high mobility channel itself and the other is the stressor for creating strained-Si channels with high carrier mobility and low effective mass, utilizing the difference in the lattice constant between Si …

2016年8月17日 · In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production.

2024年8月15日 · This article investigates a vertically grown double gate silicon channel and germanium source dopingless TFET using the charge plasma concept for enhanced analog performance. The germanium layer used in the underlap region …

2016年4月22日 · This paper explores the potential of Si/Ge tunnel FETs (TFET) in designing ultra-low power embedded memory bit cells, namely, Static Random Access Memory (SRAM) and embedded Dynamic RAM (eDRAM). A Technology CAD (TCAD)-based model of 22-nm Si/Ge TFET is designed and coupled with mixed-mode circuit simulation.