2022年5月9日 · 源漏区嵌入SiGe应变材料可以提高PMOS的速度。 它是通过外延生长技术在源漏嵌入SiGe材料，从而对沟道产生单轴压应力，改变硅价带的能带结构，降低空穴的电导有效质量。

源漏嵌入SiGe应变技术被广泛用于提高90nm及以下工艺制程PMOS的速度。 它是通过外延生长技术在源漏嵌入SiGe应变材料，利用锗和硅晶格常数不同，从而对衬底硅产生应力，改变硅价带的能带结构，降低空穴的电导有效质量。

SiGe广泛应用于90nm及以下的应力工程，利用锗硅晶格常数的不同产生的压应力，嵌入源漏区，提高了PMOS空穴的迁移率和饱和电流。 硅的晶格常数是5.43095A，锗的晶格常数5.6533A ，硅与锗的不匹配率4.1%，锗硅的晶格常数大于纯硅，在源漏区产生压应力。

Abstract—Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in

These results suggest that the <100> strained-SiGe-channel p-MOSFET can be used to achieve high-speed CMOS devices that operate at low voltages. 1. Introduction. High-speed devices require a large charging current that is obtained by either reducing their channel length or increasing their carrier mobili-ty.

SiGe has shown promise as a new channel material for PMOS type of devices. Ge offers highest hole mobility (1900 cm2/V-s) among all group IV or III-V class of materials. However Ge has issues in fabricating a good insulator, hence SiGe alloy offers an attractive alternate option.

Abstract: In the pursuit of reducing the leakage of PMOS, this research investigates methods to enhance the performance of PMOS devices through an analysis of halo dose and SiGe morphology. Experimental results highlight the critical influence of halo dose on device performance, with higher doses leading to improved outcomes.

目前常见的应变硅工艺包括 应力记忆技术 （SMT） 、 接触孔刻蚀停止层 （CESL） 、 嵌入式SiGe 、 嵌入式SiC，他们对 NMOS 和 PMOS 的不同作用分别表示如下。 SMT工艺. SMT（stress memorization technique）应力记忆技术，是一种利用覆盖层 Si3N4 单轴张应力提高90nm及以下工艺制程的应变硅技术。 Si3N4不直接对沟道引入应力，先通过高温退火把应力传导源漏和栅极，通过它们将应力传递到沟道，最终用酸去除Si3N4薄膜，应力会形成记忆作用留下来。 传统 …

2020年7月10日 · 随着超大规模集成电路技术的迅速发展，器件尺寸的不断缩小，为了提高pmos的性能，锗硅(sige)作为pmos源漏区的应力源，被引进到cmos的制造工艺中，其通过向沟道处提供压应力，减小空穴的有效质量来增加空穴迁移率从而被广泛使用。

In this paper, we present the development of a new 14nm SiGe process that is designed to improve with-in-wafer uniformity to eventually improve Electrical parameters, parametric limited yield and overall average yield.