In April 2023, at its Technology Symposium, TSMC introduced two more processes of its 2 nm technology platform: "N2P" featuring backside power delivery and scheduled for 2026, and "N2X" for high-performance applications.

TSMC 2nm (N2) technology development is on track and made good progress. N2 technology features the company’s first generation of nanosheet transistor technology with full-node strides in performance and power consumption. Volume production is expected in 2025. Major customers completed 2nm IP design and started silicon validation.

2024年4月25日 · At a high level, TSMC's 2 nm plans remain largely unchanged: the company is on track to start volume production of chips on it's first-generation GAAFET N2 node in the second half of 2025,...

2024年12月14日 · TSMC revealed additional details about its N2 (2nm-class) fabrication process at the IEEE International Electron Device Meeting (IEDM) earlier this month. The new production node promises a 24 to...

2024年5月30日 · TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of...

2025年3月4日 · TSMC is currently expected to begin mass production of 2 nm chips in Taiwan in the second half of 2025, followed by 1.6 nm chips in 2026. Taiwan government officials have previously said...

2025年3月25日 · TL;DR: TSMC's 2nm process node is set for mass production in late 2025, with Apple as the first customer for its A20 Pro chip in the iPhone 18 Pro series in 2026. Initial 2nm wafers will arrive at ...

46 分钟之前 · AMD today announced its next-generation AMD EPYC processor, codenamed "Venice," is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2 nm (N2) process technology. This highlights the strength of AMD and TSMC semiconductor manufacturing partnership to co-optimi...

8 小时之前 · AMD Achieves First TSMC N2 Product Silicon Milestone "AMD Chair and CEO, Dr. Lisa Su and TSMC Chairman and CEO Dr. C.C. Wei holding a wafer of the next gen AMD EPYC CPU, codenamed 'Venice ...

2024年12月17日 · TSMC's N2 technology achieves a record-breaking 2nm SRAM density of approximately 38 megabits per square millimeter (Mb/mm²), an 11% improvement over the N3 process. This improvement is attributed to the superior transistor architecture and design flexibility provided by the GAA nanosheet transistors, which significantly enhance SRAM ...