2022年12月22日 · 本报告将详细介绍 N5、N4、 N3B 和 N3E 的各种间距、特性和 SRAM 单元 尺寸。 几周前， 台积电 在 IEDM 会上展示了有关其 N3B 和 N3E、3nm 级工艺节点的许多细节。

2023年4月26日 · As revealed today by TSMC, N3P will be an optical shrink of N3E, offering enhanced performance, reduced power consumption, and increased transistor density compared to N3E, all while...

在其 2022 年台积电技术研讨会上，台积电谈到了将在未来几年推出的四种N3 衍生制造工艺（总共五个3 纳米级节点）—— N3E 、N3P、 N3S 和 N3X。 这些 N3 变体旨在为超高性能应用提供改进的工艺窗口、更高的性能、增加的晶体管密度和增强的电压。 所有这些技术都将支持FinFlex，这是TSMC 的“秘密武器”，极大地增强了他们的设计灵活性，并允许芯片设计人员精确优化性能、功耗和成本。 *请注意，台积电在2020 年左右才开始分别发布针对模拟、逻辑和 SRAM 的晶体 …

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3 nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm 2 for N3 and 0.021 μm 2 for N3E (same as in N5).

TSMC’s 3nm process is the industry’s most advanced semiconductor technology offering best power, performance, and area (PPA), and is a full-node advance from its 5nm generation. Following N3 technology, TSMC introduced N3E and N3P, enhanced 3nm processes for better power, performance, and density.

TSMC 2022年的技术讨论会上，分析了四种N3衍生工艺（共计5个3nm节点）： N3E，N3P， N3S 和 N3X，这些N3工艺将带来更高的性能、更高的晶体管密度和更高的电压.

2024年5月15日 · TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning.

2022年12月21日 · Unlike the previous nodelets that TSMC has launched for its N7 and N5 family of nodes, N3E is not IP-compatible with N3B IP. This means that IP blocks have to be reimplemented. As such, many companies, such as GUC, have chosen only to implement their IP on the more long-lasting N3E node. N3P will be the follow-up node to N3E.

2022年6月20日 · 在2022年的TSMC技术研讨会上，谈到了四种N3衍生出的制造工艺（共5个3nm级节点），N3E、N3P、N3S和N3X将在未来几年内推出。 这些N3衍生版预计将为超高性能应用提供更好的工艺窗口、更高的性能、更高的晶体管密度和更大的电压。

2022年4月22日 · TSMC's N3 is set to bring in full node improvements over N5, which includes 10% ~ 15% more performance, 25% ~ 30% power reduction, and an up to 1.7X higher transistor density for logic.