2024年5月15日 · Chip-on-Wafer-on-Substrate (CoWoS) is a two-point-five dimensional integrated circuit (2.5D IC) through-silicon via (TSV) interposer-based packaging technology designed by TSMC for high-performance applications.

SoIC-X wafer-on-wafer technology creates heterogeneous and homogeneous 3D silicon integration through a wafer stacking process. The tight bonding pitch and thin Through Silicon Vias (TSV) enable minimum parasitics for better performance, lower power, less latency, and a smaller form factor.

2012年，TSMC与Xilinx一起推出了当时最大的FPGA，它由四个相同的28 nm FPGA芯片并排安装在 硅中介层 上。他们还开发了硅通孔（TSV），微凸点和再分布层（re-distribution-layer：RDL），以将这些构件相互连接。

TSMC 3DFabricTM technology platform continues packaging envelop scale-up, and 3D stacking interconnect density scale-down to drive energy efficient performance. Thermal wall could also be addressed for more 3D stacking by new micro-cooling systems- ISMC and DWC.

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer.

TSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip.

3d封装与硅通孔tsv工艺技术，通过硅通孔（tsv）铜互连的立体（3d）垂直整合，目前被认为是半导体行业最先进的技术之一。 硅片通孔（ TSV ）是三维叠层硅器件技术的最新进展。

TSMC’s off-chip interconnect technologies continues to advance for better PPACC: Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI; Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI

Currently, an interposer up to 3.3X-reticle size (or ~2700mm 2) is ready for production. The CoWoS ® -L and CoWoS ® -R platform are recommended for larger than 3.3X-reticle interposer sizes. Different interconnect options provide more flexibility integration to …

2015年4月7日 · 针对雷射钻孔与填充TSV穿孔、暂时性晶圆键合与去键合，以及硅穿孔露出等关键制程步骤进一步降低成本，是3D IC得以落实大众市场的另一个必备条件。 第2页：降低材料与工艺成本. 第3页：精确硅穿孔露出 {pagination} 降低材料与工艺成本