A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB.

FD-SOI消除了闩锁效应(Latch up 是指CMOS晶片中, 在电源power VDD和地线GND(VSS)之间由于寄生的PNP和NPN双极性BJT相互影响而产生的一低阻抗通路, 它的存在会使VDD和GND之间产生大电流。

UTB-DG SOI（Silicon On Insulator）T-FinFET在强倒易区工作，其电子的有效迁移率（carrier mobility, μ_eff）对于器件性能至关重要，尤其是在高速和高压应用中。 作者们在论文中提出了一个解析的有效场...

2025年2月1日 · This paper presents and optimizes for the first time the design of UTB SOI MOSFET and its connection method for 2.45 GHz weak energy density harvesting, and optimizes the device structure parameters by Sentaurus TCAD software, so that the device exhibits the desired characteristics of high forward bias current and low reverse leakage current.

2005年10月24日 · Abstract: The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It is shown that the mobility in [110] UTB pMOSFETs, which is much higher than the universal curve in conventional (100) pMOSFETs, is ...

同年该团队又提出了超薄体-绝缘体上硅UTB-SOI（FD SOI）减少寄生电容，晶体管的工作速度更快， 性能 更好。 这里着重对这两种结构进行详细阐述，使读者能够对这一技术革新有更好的了解。 传统MOS晶体管结构中，以NMOS为例,在栅极上施加一定电压，栅极一侧聚集大量正电荷，这些电荷将会排斥p型衬底中的空穴，留下带有负电荷的受主离子，产生耗尽区域。 随着所加电压值增大到某一特定值，p型衬底表面会由于强大的库仑力出现被正电荷吸引的电子，这一现象称 …

A self-aligned thin body SOI device has previously been proposed for suppressing the short channel effect. UTB structure can eliminate the punchthrough path between source and drain and provide a more evolutionary alternative to the double …

2016年2月3日 · This paper demonstrates the integration of fully depleted ultra thin-body Silicon on Insulator MOSFET (FD UTB SOI n and p-MOSFET) into CMOS inverter circuit. The proposed MOS device shows the better Ion to Ioff ratio, lower subthreshold slope and low threshold voltage at 50 nm gate length.

通过分析utb soi器件的硅膜厚度、侧墙宽度等结构参数对器件交流特性的影响,对器件结构进行 了优化. 最终针对UTB SOI MOSFET结构提出了一种缓解速度和功耗特性优化之间矛盾的方法,从而实现了结构参

2015年10月27日 · 通过分析utb soi 器件的硅膜厚度、侧墙宽度等结构参数对器件交流特性的影响,对器件结构进行 了优化. 最终针对UTB SOI MOSFET结构提出了一种缓解速度和功耗特性优化之间矛盾的方法,从而实现了结构参