2023年2月27日 · This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van ...

2022年10月14日 · In this study, we report the realization of steep-slope impact ionization field-effect transistors (I 2 FETs) based on a gate-controlled homogeneous WSe 2 lateral junction. The devices showed...

Abstract: This study introduces a novel hybrid p-doping strategy, integrating tungsten oxide (WO x) charge transfer and nitric oxide (NO) molecular doping with wafer-scale CVD grown monolayer tungsten diselenide (1L-WSe 2).

2025年2月4日 · WSe 2, as the primary material for p-channel FETs, is suffering from intrinsic atomic defects and extrinsic defects during metal deposition, making it difficult to form high-quality metal–semiconductor contact interfaces. This leaves significant space for improvement in the performance of p-channel FETs.

In an field-effect transistor (FET) with few-layer WSe 2, a charge carrier mobility up to 70.1 cm 2 ∙V −1 ∙s −1 and an outpaced 10 6 ON/OFF current ratio was achieved with an Al 2 O 3 top-gate dielectric. 311

2014年6月20日 · This work presents a systematic study toward the design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayer WSe2.

2022年5月16日 · The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.

Abstract: In this work, we demonstrate high-performance bilayer WSe2 pFETs by direct CVD growth and fabrication on SiO2 substrate without a transfer process.

2020年4月30日 · Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform.

2018年10月31日 · Abstract: P-channel WSe 2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe 2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe 2 served as the channel for the electrostatics integrity of the FET.