The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles.

The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important.

View datasheets for XC9500 CPLD Family by Xilinx Inc. and other related components here.

目前，Xilinx公司XC9500系列CPLD的tpd可达4ns， 宏单元 数达到288个，系统时钟可达到200MHz。 XC9500器件支持PCI总线规范和JTAG 边界扫描 测试功能，具有在系统可编程功能能力。

XC9500 CPLD 系列提供了面向高性能通用逻辑集成的高级在系统编程和测试能力。 所有器件都可实现最小为 10,000 编程/擦写周期的在系统编程。 This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages. 本技术文档介绍了各种工作条件下的 I/O 行为。 它介绍了如何使用不同的终端模式，如何理解阈值，以及加载是如何影响 I/O 的。

The XC9500XL 3.3V CPLD Automotive IQ product family is targeted for leading-edge, high-performance, low-voltage extended industrial (–40°C to +125°C) applications. Power dissipation in CPLDs can vary substantially depend-ing on the system …

XC9500系列CPLD器件的t PD最快达3.5ns，宏单元数达288个，可用门数达6400个，系统时钟可达到200MHz。 XC9500系列器件采用快闪存储技术（FastFLASH），与E2CMOS 工艺相比，功耗明显降低。

XC9500 系列器件 功能块利用乘积项和的形式实现逻辑。 功能块 的输入来自快速连接矩阵，有 36 个输入信号送到可 编程的"与"阵列构成了 90 个乘积项。

The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.

The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-port is also included on all family members.