This paper presents the industry's smallest Embedded Dynamic Random Access Memory (eDRAM) implemented in IBM's 22nm SOI technology. The bit cell area of 0.026µm 2 …

A 24 kbit GC-eDRAM macro implementing the proposed 3T GC was fabricated in 28 nm FD-SOI technology, resulting in the highest density logic-compatible embedded memory fabricated in …

2024年2月22日 · A novel single-transistor dynamic random access memory (1T-DRAM) named IS-DRAM (in-situ sensing DRAM) which combines non-destructive reading with compact …

2020年5月14日 · IBM adopted a new micro-architecture for Power9 such as 14 nm FD-SOI FinFET combined with a deep trench capacitor for eDRAM L3 cache memory, which enables …

2020年8月10日 · Gain cell embedded DRAMs (GC-eDRAM) are a potential alternative for conventional static random access memories thanks to their attractive advantages such as …

仿真结果表明，与采用 28-nm fd-soi 技术的 4t 全 nmos gc-edram 单元相比，所提出的 5t 位单元（0.7 v）可实现超过 13 倍的数据保留功率和 10 倍的面积减少。 EN

2019年11月1日 · A 128-kbit GC-eDRAM macro utilizing the proposed boosting circuitry has been fabricated in a 28-nm FD-SOI technology, demonstrating an $11.3\times $ DRT improvement …

FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications Abstract: A Capacitorless IT-DRAM cell using gate …

2022年5月31日 · The authors in presented a 4T GC-eDRAM memory (Fig. 1(d)), based on an nMOS-only bitcell with internal feedback to provide efficient operations in the 28 nm FD-SOI …

2017年6月25日 · This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long …