ATMX150RHA is manufactured on a 150 nm, five-metal-layer and thick-metal-layer SOI CMOS process intended for use with a supply voltage of 1.8V for core and 2.5/3.3/5V for periphery. This ASIC platform is supported by a combination of state-of-the-art third-party and proprietary design tools from Synopsys®, Mentor® and Cadence®.

On Insulator (SOI) CMOS process offers high levels of integration, minimized power dissipation and high performance to enable reliable, cost-effective products for space military and commercial markets. Our customers benefit from Honeywell’s high-reliability ASIC, System-on-Chip (SoC) and MultiChip Module solutions

Honeywell's S150 150 nm Silicon on Insulator (SOI) process enables ASICs with approximately 15 million usable gates. This is achieved using a fully planarized 6 or 8-layer metal process. HX5000 is designed for use over the full military temperature range while operating in harsh radiation environments.

Atmel-41059 V1.1-AERO-Rad-Hard 150nm SOI CMOS Cell-based ASIC for Space Use–AdvanceDatasheet_08/2016 3 1 Overview The ASIC “ATMX150RHA Design Manual” presents all the required information and flows to design a mixed-signal ASIC for space applications, allowing users to be trained on Atmel specific or standard commercial tool

150nm silicon-on-insulator CMOS (S150) technology. It is designed for use in low voltage systems operating in radiation environments. The SRAM operates over the full military temperature range and requires a core supply voltage of 1.8V and supports I/O supply voltages of 2.5V and 3.3V. Honeywell’s state-of-the-art S150 technology is

2014年11月13日 · soi工艺已被验证可以有效地抵抗单粒子 翻转效应和免疫闩锁效应，这些优势简化了 制造流程、提高了密度、降低了多种寄生电

In this paper, we review the process and layout optimization of thin-film (150nm) SOI SiGe HBTs covering a wide range of f -BV tradeoffs, i.e. from ~150GHz f to ~8V BV . We have shown that a SiGe HBT with bulk-like f -BV trade-off can be built on a CMOS compatible SOI substrate.

77K 150nm SOI Process qualification following MIL and ESCC standards Mixed-signal solutions target ASICS, ASSPs, mixed MicroControllers and SoC to miminize cost, area, power consumption

2011年5月12日 · Abstract: Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology.

Inherent hardness of SOI to dose rate upset and latchup has leveraged major developments of SOI technologies. TID hardness for up to the 150nm node was addressed by process hardening. Inherent hardness of 45nm and 32nm technologies reduced the need for TID hardening.