High performance Si-MoS 2 heterogeneous embedded DRAM
2024年11月12日 · A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the short retention issue in conventional gain cell...
《嵌入式存储器架构、电路与应用》----学习记录 (二)_传统dram
2023年6月2日 · 日本的半导体能源实验室从器件角度出发，提出用氧化物半导体场效晶体管 (OSFET)结合传统CMOS工艺设计了2T1C的GC eDRAM，电路结构如图3-22所示。 除了改良单元结构来优化eDRAM的 性能 以外，提出新的eDRAM架构也是一种当前热门的研究方向，其中最具代表性的是Micron提出的混合存储立方体 (HMC)架构，如图3-23所示。
A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T …
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported.
A logic 2T gain cell eDRAM with enhanced retention and fast …
2012年10月29日 · A logic-process embedded DRAM with 2T multi-Vth PMOS gain cell with one high-Vth for retention enhancement and one low-Vth transistors for fast read speed is proposed. To improve the write speed, the write back step and sense step are separated, and the write before sense schemes are adopted to improve write speed and suppress the noise ...
Novel 2T gain cell with enhanced retention time for embedded …
A high performance 2T gain cell memory device is demonstrated for the first time in 0.13μm CMOS technology. A novel asymmetric source and drain doping profile combined with high threshold voltage (Vt) scheme for the write transistor is introduced to reduce the cell leakage and then improve data retention characteristics.
1+1>2：复旦大学团队“硅基-二维”异质嵌入式DRAM，开创二维半 …
2024年12月1日 · 2t-edram能够在写入字线电压为0 v时将数据保持时间延长至6000秒，超过传统的硅基dram多个数量级，同时兼具5纳秒的快速写入速度，完全满足高算力的高层缓存应用的要求。
1+1>2：复旦大学团队“硅基-二维”异质嵌入式DRAM，开创二维半 …
2024年12月1日 · 2t-edram能够在写入字线电压为0 v时将数据保持时间延长至6000秒，超过传统的硅基dram多个数量级，同时兼具5纳秒的快速写入速度，完全满足高算力的高层缓存应用的要求。
Abstract — A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously …
2T DRAM cell operation. | Download Scientific Diagram
As seen in Chap. 2, gain-cell (GC) embedded DRAM (eDRAM), or GC-eDRAM in short, is an interesting alternative to static random-access memory (SRAM) and 1-transistor-1-capacitor (1T-1C) eDRAM...
Abstract- A gain cell embedded DRAM (eDRAM) in a 65nm LP process achieves a 1.0 GHz random access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to …