Aug 14, 2020 · Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or “X-Cube”, allowing chip-stacking of SRAM dies on top of a base logic die through TSVs.

To fulfill the memory requirements, Samsung Foundry proposed a three-dimension (3D) static random access memory (SRAM) stacking solution (SAINT-S, Samsung Advanced INterconnection Technology with SRAM).

Aug 16, 2021 · The SRAM die has been designed to sit on top of the L3 cache of the processor, connecting by both hybrid bonding and TSVs (through-silicon vias), and dummy silicon is added to provide strength and give a uniform top surface to the assembly.

Samsung 'X-Cube' enables industry-first 3D SRAM-logic working silicon at 7nm and beyond. Bandwidth and density can be scaled to suit diverse design requirements.

We introduce two dis-tinct design methodologies for 3D SRAM arrays - Wordline and Bitline folding. Through post-layout simulations conducted on ar-rays with capacities of 2kB (256WLx64BL) and 8kB (512WLx128BL), our 3D designs exhibit superior performance metrics.

3D-Split SRAM: splitting the WL/BL of a SRAM block across 3D tiers. Reduction in BL/WL RC 2D & 3D configurations of 64Kb L1 cluster. Simulation in 12nm @SS/(VNOM-10%)/-40 C. Wire delay ~200ps/mm. RC parasitics of 3D-BEOL Access time vs Area for 2D and 3D-split macros. -identify opportunities of 3D-BEOL RC improvement. Default.

enable ultra-high density 3D SRAM based on monolithic 3D integration. Our target technology offers one tier of NMOS devices, another for PMOS devices, and nano-scale inter-tier vias.

Abstract— This paper illustrates the performance ad-vantages of 3D integrated circuits with two specific exam-ples, namely 3D-FPGA and 3D-SRAM. Through strategic modification of the architectures to take advantage of 3D, significant improvement in speed and reduction in power consumption can be achieved.

perform physical design of bank-level 3D SRAM. We show that a tradeoff exists in terms of reliability and performance for 3D SRAMs. We also show the impact of via-first vs via-last TSVs on the layout quality of 3D SRAM designs. All our results are based on GDSII based layouts.

Jul 20, 2021 · True next-gen 3D chip stacking may be right around the corner, as researches from the Institute of Microeletronics (IME) have just achieved a technology breakthrough that enables up to four...