Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and ...

• Decision Feedback Equalization • Examples • The Whitened Matched Filter and Zero Forcing • FIR Implementation L15: 2

–DFE-IIR based equalization approach • DFE-IIR Rx performance demonstrated over range of channels –Smoothly varying PCB channels (>20 dB loss) –Legacy backplane: 16” Tyco channel (27 dB loss) –Emulated carrier channels, e.g., 40 mm (22 dB loss) @ 8.9 Gb/s, 1.9 mW/Gbps

判决反馈均衡（Decision feedback equalizer，DFE），顾名思义，通过“判决”和“反馈”两个操作，实现对信号内噪声的均衡。 要理解DFE的功能，就不得不引入码间串扰（intersymbol interference，ISI）这一现象。

the number of DFE feedback signals at the summing circuit, an infinite-impulse-response (IIR) filter is adopted to subtract the residual post-cursor ISIs after the first one [7]. Such a careful selection of the circuit techniques made a highly energy-efficient equalizing receiver possible with …

Abstract: To ensure the signal integrity over a lossy channel, an analog equalizer and/or a decision-feedback equalizer (DFE) are widely adopted in high-speed data transmission. An adaptive analog equalizer or adaptive DFE is also attractive to compensate the frequency-dependent loss due to the different channel lengths and environment variations.

decision feedback equalizer (DFE) [2]–[7] has been widely recognized as an effective approach because it reduces signal distortion without amplifying noise or crosstalk. In order to apply DFE techniques to silicon carrier channels, the DFE design must address the fact that long silicon carrier channels

Abstract: This brief presents a quarter-rate 1 finite impulse response and 1 infinite impulse response (IIR) direct decision feedback equalizer (DFE). The proposed non-time-overlapping data generation enables the elimination of all two-stacked clocked transistors in the 4:1 current-mode-logic multiplexer of conventional quarter-rate IIR DFEs.

Abstract—Decision feedback equalizer (DFE) architectures with varying numbers of discrete-time taps and continuous-time infinite impulse response (IIR) filters are compared for use in typical wireline channels. In each case, the DFE coefficients are optimized to minimize a cost function that equally weights both jitter and vertical eye opening.

1 IIR-tap DFE to efficiently cancel long-tail ISI. A bang-bang phase detector (BBPD) PLL-based CDR allows for clock recovery with only one per-slice edge sampler and utilizes static phase interpolators for eight-phase data and edge clock generation. Utilizing the edge samplers, the DFE adaptation scheme of [3] is extended for PAM4