A novel gate-coupled NMOS (gcNMOS) structure for electrostatic discharge (ESD) protection is proposed in this paper, which can be realized in an advanced 22-nm full-depleted silicon-on-isolation (FD-SOI) technology.

Fig. 6 Design comparison of ggNMOS and gcNMOS ESD structures by TCAD: (a) simulation schematics, (b) ggNMOS ESD discharging I-V curve (Inset: hot spot), (c) ggNMOS ESD discharging in t-domain, and (d) gcNMOS ESD discharging I-V characteristics (Inset: V …

Jan 10, 2018 · Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS).

Abstract: A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

NMOS主要有两种 ESD防护 应用：一种是之前讲的 GGNMOS，另一种是GCNMOS（Gate Coupling NMOS）。 现阶段也已经出现了（Bulk Coupling NMOS），接下来这两种ESD防护器件都会进行讲解。 GCNMOS的工作原理与GGNMOS不同，GGNMOS是利用 体寄生三极管 的开启进行ESD静电流的泄放通路，而GCNMOS则利用了NMOS器件的沟道作为泄放通道。 …

Dec 30, 2023 · GGNMOS (Grounded Gate NMOS) 和 GCNMOS (Grounded Grid NMOS) 是两种常见的 ESD (静电放电) 防护电路设计。 它们的主要目的是在输入/输出 (I/O) 端口提供一个放电路径，以防止由于静电放电而产生的过高电压损坏电路。

GCNMOS就是在gate和drain之间加一个MOS电容，当漏级有一个较大的能量时，会通过Cout将gate给couple起来，这个时候沟道会通过一个较小的电流I1，该NMOS会弱导通，注意如果gate大于Vth的话，NMOS完全导通的话，管子往往承受不了太大的沟道电流，有可能造成烧毁。 当gate被couple起来后，衬底中的电子会往沟道方向移动，会形成一个较小的从沟道往P的电 …

Dec 20, 2012 · GCNMOS 是用來改善 GGNMOS 無法 uniform turn-on 的缺點. 透過 Cgd 的 coupling 使的 GCNMOS 的gate電壓稍為提高, 可以降低 snapback trigger 電壓, 使更多的nmos finger 有機會 uniform turn-on, 進入snapback region,啟動 nmos 下寄生的 lateral BJT.排掉ESD電流.

Displacement current through the Drain/Bulk junction causes a Vbe spike in the parasitic NPN in ggNMOS. Avalanche current in Drain/Bulk junction is enhanced by the Vbe spike, which eventually results in a lower trigger Vt1. Higher CJC and shorter rise time (higher dV/dt) cause bigger Vt1 reduction.

multi-finger gate-grounded NMOS (GGNMOS) devices are widely used as ESD protection structures due to the effectiveness of the parasitic lateral NPN bipolar junction transistor in handling high ESD current. However, it has been reported that, sometimes, a multi-finger GGNMOS is not uniformly turned on under ESD stress [3]-[6].