This paper presents an efficient error-correction-code (ECC) scheme which is designed to enhance the Reliability, Availability, and Serviceability (RAS) features and save area for HBM3 DRAM, the latest-generation technology of high bandwidth memory (HBM).

However, recent soft error experiments on HBM2 reveal that DRAM frequently experiences multi-bit errors, necessitating a stronger OD-ECC solution. This paper introduces a novel OD-ECC, EPA ECC, specifically designed to correct frequently-observed multi-bit error patterns.

HBM IP提供了一系列ECC相关选项： Enable ECC Bypass- ECC错误校验和纠正功能关闭。 Enable ECC Correction- 对于单bit 的ECC错误进行纠正。 Enable ECC Scrubbing- 使能擦洗功能。 它从HBM读取数据，检测并纠正单bit ECC错误，再写回到原来的位置。

The HBM Memory Controller IP is highly efficient, highly configurable single channel memory controller which with its ‘2-command compare and issue’ algorithm reduces number of dead cycles and increases data transfer with HBM memory to achieve high bandwidth.

One of the biggest changes for RAS in HBM3 is how error correcting code (ECC) is handled. Let’s start by examining the host side of ECC. HBM2E provides an option for the host to enable a sideband ECC implementation by allowing the DM signal …

Optional data error correcting code (ECC) support per channel. One differential clock for commands, address, and data. (Unlike GDDR5(X), which has half rate clocks for commands and addresses.)

2024年2月20日 · NPUx芯片出现degrade告警，但告警码指向单device出现多BIT 片上内存 ECC错误，典型告警码包含以下两种： 0x80E18401：单个Device的 片上内存 多bit ECC隔离地址记录超过16个，如 图2 所示。

In this paper, we propose Sparrow ECC, a lightweight but stronger HBM ECC technique for less refresh operations while preserving inference accuracy.

HBM内存颗粒巡检多bit ECC错误. 故障解释/可能原因. HBMC巡检（Patrol Scrubbing和Demand Scrubbing）触发的多bit ECC错误，可能原因为HBM颗粒部分失效、HBM无法正常保持数据等. 故障影响. 1. 启动过程中访问到错误地址，可能会启动失败. 2.

服务器重启后，执行npu-smi info -t ecc -i <device_id> 命令，查询 片上内存 多比特ECC故障信息， 查看“HBM Double Bit Isolated Pages Count”计数值。 收集该服务器近期发生的 片上内存 多比特ECC次数和时间信息、 片上内存 多比特ECC隔离计数值，根据 结论、解决方案及效果 ...