Silicon Interposer (2.5D) is the incumbent technology of choice. Potentially lower cost, fine pitch interconnect wafer-level and substrate based technologies are emerging .

2023 年1月，公司XDFOI™ Chiplet高密度多维异构集成系列工艺已按计划进入稳定量产阶段，可以将有机重布线堆叠中介层厚度控制在50μm以内，微凸点（µBump）中心距为 40μm，并可集成多颗芯片、高带宽内存（HBM）和无源器件，实现最大封装体面积约为 1500mm²的系统 ...

Higher BW density (2x): Superior line density due to fine pitch RDL. Better power efficiency (0.03x PDN impedance): Simplified and low profile structure (without substrate or PCB).

HBM== High Bandwidth Memory 是一款新型的CPU/GPU 内存芯片（即 “RAM”），其实就是将很多个 DDR芯片 堆叠在一起后和GPU封装在一起，实现大容量，高位宽的DDR组合阵列。先看个平面图：

2024年4月26日 · hbm是gddr的一种，定位在处理器片上缓存和传统dram之间，兼顾带宽和容量，较其他存储器有高带宽、低功耗、面积小的三大特点，契合ai芯片需求。hbm不断迭代，从hbm1目前最新到hbm3e，迭代方向... 查看详情

2024年3月1日 · HBM3E技术是高带宽内存（High Bandwidth Memory）标准的最新扩展版本，相较于前代HBM3，它在多个关键性能指标上实现了显著提升，主要面向需要极高数据传输速率和大容量内存的应用场景，比如高性能计算、人工智能（AI）和高端图形处理等。

Now Samsung Electronics is ready for bump testing with this solution. This state of the art 3D-stacked DRAM uses TSV technology and has grid array of 4942 microbumps at 55um pitch as its signal terminal. Until now, there was no proper solution for bump probing such a fine pitch and high density as well in the market.

2020年11月17日 · How Does Advanced Packaging (HBM) Impact Test? Complexity! Spatial/Mechanical – Higher Density • Smaller pitches and higher probe counts • More delicate contacts (new materials) Electrical – Higher Performance • Higher clock speeds, nearing RF frequencies • Increased current per contact, higher power density

2021年10月25日 · Going forward, vendors want to develop HBM modules and 3D packages with bumps below 40μm pitches, enabling more I/Os and bandwidth. Chip customers could develop advanced packaging using finer bumps or go with copper hybrid bonding.

HBM is a breakthrough memory solution for performance, power and form-factor constrained systems by delivering high bandwidth, Low effective power & Small form factor