2024年9月27日 · The Scalable Matrix Extension (SME) has been announced for the Arm architecture in 2021 and Apple's M4 chip is the first to support SME. This paper presents an in-depth study of SME on M4. Our microbenchmarks determine the maximum floating-point and fixed-point throughput of M4's SME acceleration and study the …

Hello SME! Generating Fast Matrix Multiplication Kernels Using the Scalable Matrix Extension Abstract: Modern central processing units (CPUs) feature single-instruction, multiple-data pipelines to accelerate compute-intensive floating-point and fixed-point workloads.

M4 is the first publicly available silicon supporting Arm’s Scalable Matrix Extension (SME). SME has been eagerly awaited by the HPC community for quite some time now, and this page is dedicated to providing information about M4’s SME support.

fixed-point throughput of M4’s SME acceleration and study the achievable bandwidth for transfers to and from the matrix regis-ters. Furthermore, we used the insights gained to design a just-in-time code generator for SME-based small matrix multiplications. The results presented show that M4’s SME support is FP32-

We benchmark the best case by hot-looping over vector instructions in the case of Neon and streaming SVE, and over outer-product instructions in the case of AMX and SME. The benchmarks are written to avoid possible inter-instruction dependencies. For now, we limit our considerations to FP32 arithmetic.

The Scalable Matrix Extension (SME) was announced for the Arm architecture in 2021, and Apple's M4 chip is the first to support SME. This paper presents an in-depth study of SME on M4. Our microbenchmarks determine the maximum floating-point and fixed-point throughput of M4's SME acceleration and study the achievable bandwidth for transfers to ...

2024年9月3日 · Armv9 架构上的可伸缩矩阵扩展 (SME) 显著提高了 Arm CPU 对现有人工智能 (AI) 和机器学习 (ML) 工作负载的处理能力，从而在各种 AI 驱动的设备和应用中带来速度更快、响应更灵敏的用户体验。

2025年2月11日 · The Scalable Matrix Extension (SME) has been announced for the Arm architecture in 2021 and Apple's M4 chip is the first to support SME. This paper presents an in-depth study of SME on M4. Our microbenchmarks determine the maximum floating-point and fixed-point throughput of M4's SME acceleration and study the …

In mid-2021, Arm announced the first technical details of its upcoming Scalable Matrix Extension (SME). SME is based on an outer-product engine and its instructions are available as part of the Arm A-profile A64 Instruction Set Architecture. At its core, SME is very similar to Apple’s AMX and programming it is like meeting an old friend.

To maximize read and write bandwidth, loading and storing to and from the matrix registers must be done in two steps. Our just-in-time generated small matrix multiplication kernels outperform the vendor-optimized BLAS implementation in almost all tested configurations.