2015年8月19日 · A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm 2 deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line.

Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) [1] of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM ...

2005年1月1日 · The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously sepa...

该工艺具有超高密度DTC eDRAM。 十多年来，eDRAM一直是IBM的秘密武器。 即使在其 14nm工艺 中，其单元尺寸也仅为0.0174μm²。 目前， 台积电 在尚未量产的5纳米工艺中的SRAM单元为0.021μm² 。 这使得IBM的14 nm eDRAM位单元的密度比迄今为止最密集的5nm SRAM单元还要高出大约20％。 那么，IBM是如何使eDRAM缓存的密度几乎翻倍的？ 这个要归功于IBM的物理设计团队。 事实证明，到现在为止，它们的14 nm节点 已经相当不错，并且位线和字线上的开销 …

2020年5月14日 · IBM adopted a new micro-architecture for Power9 such as 14 nm FD-SOI FinFET combined with a deep trench capacitor for eDRAM L3 cache memory, which enables …

This paper presents the industry's smallest Embedded Dynamic Random Access Memory (eDRAM) implemented in IBM's 22nm SOI technology. The bit cell area of 0.026µm

This paper presents the industry's smallest Embedded Dynamic Random Access Memory (eDRAM) implemented in IBM's 22nm SOI technology. The bit cell area of 0.026μm2 achieves ∼60% scaling over the previous generation with deep trench (DT) capacitance optimized for performance and retention requirements.

2015年3月19日 · IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without ch

The 12-core 649mm2 POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3].

2023年6月2日 · GC eDRAM是一种6T SRAM和1T1C eDRAM折中选择的产物，它结合了SRAM (与数字CMOS技术兼容)和1T1C eDRAM (高存储密度)的优点，同时规避了SRAM (单元面积大)和1T1C eDRAM (破坏性读取、回写操作和需要特殊工艺步骤)的缺点。