2025年2月10日 · ana_mfn = readl_relaxed(pll->base + PLL_STATUS); ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn); return 0;

2024年9月23日 · One of the existing values in the imx_fracn_gppll_rate_table is 10x. I tried to use that, by setting my clock rates in the device tree to the following: assigned-clock-rates = …

System Manager firmware for i.MX processors. Contribute to nxp-imx/imx-sm development by creating an account on GitHub.

2022年2月23日 · > > + mfn = (pll_numerator & PLL_MFN_MASK) >> PLL_MFN_SHIFT; > Have a look at FIELD_GET/FIELD_PREP, it really makes setting and reading > fields easier and nicer …

u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); u32 div = readl_relaxed(pll->base) & pll->div_mask; + u64 temp64 = …

- Cast result of 'parent_rate * mfn / mfd' to unsigned long instead of u32. - Clarify how this issue was discovered in the commit message. - Rebased on Linux 4.8. Changes since v1: - Use …

MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This is a just sign bit. This patch makes different calculation for i.MX27.

i.MX Linux kernel. Contribute to nxp-imx/linux-imx development by creating an account on GitHub.

My board uses mipi-dsi display and works fine with Mickledore. When I upgrade to Scarthgap, the display timing is off. All clock tree timings look identical (according to …

2025年2月10日 · Set MFD/MFN to 0 instead, so the table lookup will match. See i.MX93 RM section 74.5.2.1 (PLL memory map) for ARMPLL, addresses 0x40 and 0x50 are not …