2020年12月8日 · KLA’s PWG5 system, built on the industry-standard WaferSight™ platform, is the complete wafer geometry control solution for both patterned and unpatterned wafers for ≥96 layer 3D NAND devices and ≤1Xnm logic and DRAM design nodes.

Patterned Wafer Geometry (PWG) Metrology Systems The PWG ™ patterned wafer metrology platform produces full wafer dense shape, comprehensive wafer flatness and dual-sided nanotopography data for advanced 3D NAND, DRAM and logic manufacturers.

The PWG™ patterned wafer metrology platform produces full wafer dense shape, comprehensive wafer flatness and dual-sided nanotopography data for advanced 3D NAND, DRAM and logic manufacturers.

PWG5 is a single-tool solution for measuring stress-induced wafer shape, wafer shape-induced pattern overlay errors, wafer front and backside nanotopography, and wafer thickness variations.

KLA’s wafer inspection and metrology systems for advanced wafer-level packaging provide the data required for chip manufacturers to increase yield by providing traceability throughout their increasingly complex manufacturing processes.

We demonstrated a novel technique of using PWG metrology to provide improved litho control by wafer-level grouping based on incoming process induced overlay in a 19 nm DRAM manufacturing process driving towards a 2 nm overlay budget.

2020年12月10日 · KLA’s new PWG5™ patterned wafer geometry metrology system and Surfscan® SP7XP unpatterned wafer defect inspection system support development and production of advanced logic, DRAM and 3D NAND...