PCIe问世近20年，为何PCIe 6.0变化最大？有什么新特性？ - 知乎
根据PCI-SIG的介绍，PCIe 6.0主要有三大变化：数据传输速率从32GT/s翻倍至64GT/s；编码方式从NRZ 信令模式转向 PAM4信令模式；从传输可变大小TLP到固定大小 FLIT。 从PCIe的发展历史可以看到，在2017年以前，发展速度相对较慢，三、四年更新一次标准，PCIe 3.0发布后甚至等了七年才推出PCIe 4.0。 但是2017年之后，PCIe标准几乎每两年就更新一次，更新速度明显加快。 这是因为近年来，高性能计算和AI快速发展，高清视频和网络数据迅速膨胀，还有自动驾驶等 …
PHY IP for PCI Express 6.x | Synopsys
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip interfaces.
PCIe6.0/CXL3.0 | 芯动科技 Innosilicon - 您的芯片定制专家
芯动科技 PCle6.x/CXL3.0 PHY 是一款配置灵活的物理层解决方案，单通道速率高达 64Gbps。 该 PHY 支持 NRZ 速率为 2.5、5.0、8.0、16.0、32GT/s，PMA信号传输速率为 64GT/s。
PHY for PCIe 6.0 and CXL - Cadence Design Systems
Cadence ® PHY IP for PCI Express ® (PCIe ®) 6.0 is a high-performance NRZ/PAM4 SerDes designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability.
成功使用 IP 实现 64GT/s PCI Express 6.0设计 | Synopsys
可以与内置 scope 功能结合使用，通常合并入 PCIe 6.0 PHY IP，以获得对 TX 和 RX 之间更详细的理解。 要对像 PCIe 6.0 这样的新规范进行更鲁棒的系统测试，针对调试、错误注入和统计监测功能提供内置控制器支持非常重要。
PCI Express (PCIe) 6.x IP | Synopsys
5 天之前 · Synopsys IP for PCI Express (PCIe) 6.x complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and Integrity and Data Encryption (IDE) security module IP.
PCIe 6 PHY Validation - Tektronix
CXL and NVM Express ® use the PCIe physical layer (PHY) and leverage the PCIe upper layers, software stack and platform connectivity because of their simplicity and adaptability. UCIe, the latest die-to-die standard, will also build upon PCIe at the protocol layer to provide reliable data transfer, link management and CXL cache coherency.
泰克科技 | PCIe 6.0 互操作性PHY验证测试方案 - 知乎
PCIe 6.0.1引入 PAM4信号技术，实现单通道64 GT/s传输速率，x16链路双向传输达到256GB/s。 2022年，PCI-SIG宣布了PCIe 7.0规范，将数据速率提升至128GT/s，并使用1b/1b flit编码和PAM4信号技术，在16通道下实现512GB/s双向吞吐量，同时提高电源效率。
PCI Express 6.0 Specification - PCI-SIG
PCIe 6.0 technology is the cost-effective and scalable interconnect solution for data-intensive markets like Data Center, Artificial Intelligence/Machine Learning, HPC, Automotive, IoT, and Military/Aerospace. The latest draft is PCI Express Base Specification Revision 6.3 which includes 6.0 plus errata and approved ECNs.
One stack / same silicon across all segments with different form-factors, widths (x1/ x2/ x4/ x8/ x16) and data rates: e.g., a x16 PCIe 5.0 specification interoperates with a x1 PCIe 1.0 specification! PCIe technology continues to deliver bandwidth doubling for six generations spanning 2 decades! An impressive run!