其次，PLL涉及到了多个信号域之间的转换：频域（vco）、相位域（PD）、电压域（Vctrl）、电荷域（CP），而且既有模拟信号又有数字信号，既有连续信号又有离散信号（PFD工作在离散域）。

2013年1月30日 · An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations.

Abstract—An integral-path self-calibration scheme is intro-duced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO’s small signal gain varia-tions.

This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency.

有些现代双环路模拟 pll 集成于单个芯片之上，允许设计师 减少低频参考抖动，同时还能提供高频、低相位噪声输出。 这 就节省了宝贵的 PCB 电路板面积，而且允许要求不同频率的 多个器件以同一相位对齐源为时钟源。

The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop...

2022年7月12日 · In this work, a dual-loop integer PLL is proposed aimed at improving the overall phase noise performance at the PLL output. The main loop is a charge pump based conventional architecture; the auxiliary loop samples and holds the oscillator waveform in every reference cycle and compares the held voltage with a clean dc signal to correct the ...

2022年2月2日 · Abstract: To eliminate the unexpected spurs introduced by the charge pump (CP) mismatch in typical dual-path phase-locked loops (DP-PLLs), a fast calibration method incorporated in a prototype type-II PLL is presented. By enlarging the turn-on time and shrinking the charging capacitor, the CP mismatch can be amplified and detected more ...

Abstract: A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled

Both high speed and noise filtering can be obtained by combining two PLLs: a low-frequency device with narrow loop bandwidth for jitter cleaning followed by a high-frequency device with a wider loop bandwidth. Some modern dual-loop analog PLLs are integrated on a single chip, allowing designers to reduce low-frequency reference jitter while ...