2021年10月19日 · We have developed two novel gas phase SiGe etches and characterized their properties on blanket films, multilayers (ML) and integrated NS structures. Understanding the etch properties enables careful optimization of the IS etch to address the integration challenges.

2004年6月1日 · An isotropic etching process was developed in order to remove the sacrificial SiGe layer in Si/SiGe/Si stacks and thus obtain a cavity between the Si layers. This process is shown to be selective versus silicon as long as some SiGe remains, but the Si etch rate increases suddenly when the SiGe disappears.

Abstract: In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around device architectures. This novel etch involves a precisely controlled lateral SiGe etch with very high selectivity to Si.

2020年11月2日 · In this work, a selective wet etching process of Si to Si0.7Ge0.3 with TMAH solution to fabricate SiGe nanowires is systematically investigated. Initially, the 2.3% TMAH solution at 20 °C is applied for the as grown Si0.7Ge0.3/Si multilayers stack and a “rectangular” profile is achieved at the Si0.7Ge0.3 extremity due to its high ...

2019年9月16日 · Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiN x /Si 0.75 Ge 0.25 /Si) vertical nanowires. The etching solutions were formed by mixing acetic acid (CH 3 COOH), hydrogen peroxide …

2021年11月26日 · Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below.

We found that hydrogen plasma (selective Si etch to SiGe), in combination with conventional plasma etching (selective SiGe etch to Si), controls both Si-SiGe fin etched depth and fin CDs. We could also realize Si-rich surface on SiGe by using a low-temperature plasma process, which can improve SiGe/high-k interface quality in advanced CMOS.

2021年12月7日 · We conduct an atomic-level investigation on how a Ge atom impacts on the SiGe etching rate. The plasmaless dry-etching process in ClF 3 gas is considered in this study. We perform the density functional theory to model the elementary reactions of an etchant molecule fluorinating Si/Ge atom.

2021年11月26日 · We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gate-all-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by...

2019年4月1日 · Develop SiGe etchants with high selectivity to Si, SiO2, and Si3N4. Target etchants for SiGe with <30% Ge. Target Gate-All-Around (GAA) Si applications. SiGe Thickness Effects – Etch rates and interfacial Ge content. Effective at Si>>SiGe with TMAH-based chemistries. Avantor efforts unsuccessful to date.