2020年3月1日 · The microstructural characteristics of two polycrystalline silicon (poly-Si) films with different electrical properties produced by low-pressure chemical vapour deposition on top of high resistivity silicon substrates were investigated by advanced transmission electron microscopy (TEM), including high resolution aberration corrected TEM and ...

2011年10月9日 · Amorphous silicon (a–Si) films and polycrystalline silicon (poly-Si) films on glass substrates have been extensively researched for application as thin-film transistors (TFTs) integrated on liquid crystal display (LCD) panels.

An intrinsic poly-Si (i-Poly-Si) inner layer formed by crystallization annealing at 850 °C from i-a-Si:H. An i-a-Si:H was deposited using SiH 4 only. The effect of the annealing temperature on the surface passivation properties was evaluated on a symmetric sample prepared from a 175 μm-thick HF/HNO 3 -etched 156.75 mm pseudo-square n-type ...

2019年2月26日 · In the present work, we have focused to the structural characteristics of the poly-Si films grown at 413 °C where the SPC process is suppressed. To follow the morphology as well as the processes...

In this work, XRD, TEM and Raman measurements were used to evaluate poly-Si grain size of polycrystalline silicon (poly-Si) growth in a vertical LPCVD reactor. This should be considered a first step of an overall characterization of transistor poly-Si gate including implant poly doping and annealing processes as well.

2016年7月22日 · Here we have devised a novel core/shell configuration to impose confinement on the sample to circumvent early cracking during uniaxial compression of submicron-sized Si pillars. This has enabled...

摘要 利用先进的透射电子显微镜 (TEM)，包括高分辨率像差校正 TEM，研究了通过低压化学气相沉积在高电阻率硅衬底上产生的两种不同电性能的多晶硅 (poly-Si) 薄膜的微观结构特征。 和 TEM 中的自动晶体取向映射。 结果表明，多晶硅薄膜/硅衬底界面的性质是控制多晶硅薄膜电阻率的主要因素。 多晶硅/硅衬底界面的∑3孪晶型特征强烈促进了多晶硅薄膜的高电阻率和高电线性度，导致大量扩展缺陷的产生，包括堆垛层错，∑3孪晶界以及∑9晶界在该界面。 此外，在偏离其标 …

在本研究中，为了在晶圆中制造厚度小于5 nm的更薄的Si3N4膜，开发了一种采用多晶硅（poly-Si）牺牲层的新制造工艺。该工艺能够稳定地制造厚度为3 nm的Si3N4膜。使用透射电子显微镜（TEM）束在膜中制造纳米孔。

Abstract: We report the BEOL compatible poly-Si thin-film transistor (TFT) below 400°C by green laser crystallization and microwave annealing. The TEM image reveals the H f O 2 − Z r O 2 superlattice (SL-HZO) structure of the dielectric layer.

This research uses a transmission electron microscopy (TEM) approach to analyze the deterioration of the crystallinity of poly-Si placed on the textured substrate. On the textured substrate, we created a poly-Si photovoltaic film with a RMS roughness, σ of 64 nm.